The trend of the semiconductor integrated circuit technology towards larger scales and smaller feature sizes is significantly increasing the number of gates (logic elements) and flip-flops (state memory elements). As a result, test patterns applied to semiconductor integrated circuits for determining if the circuits are defective and the resulting power dissipation are increasing, and test quality is decreasing.
In particular, as power supply voltage gets lower and lower, semiconductor integrated circuits become less resistant to IR-drop during testing. IR-drop is a phenomenon that occurs when test patterns cause transitions at output logic of gates and flip-flops in a semiconductor integrated circuit, and a power supply voltage temporarily drops due to an excessive current flowing through the circuit. More specifically, a path delay related to a test response increases in accordance with IR-drop, and a timely test response cannot be obtained. In this manner, the false testing problem is getting worse and worse, resulting in false test responses caused by timing violations. As a result, the proportion of defect-free devices for all devices manufactured (i.e., yield) of semiconductor integrated circuits is decreasing. The false testing problem is specifically significant in two-pattern testing, which needs to have strict timing requirements. Two-pattern testing herein is defined as testing that applies two patterns (v1 and v2) shown in FIG. 7, for example, to a semiconductor integrated circuit for detecting timing-related defects.
To prevent false testing, IR-drop must be reduced during testing. Therefore, test patterns capable of reducing the number of gates, which cause output logic transitions, are required. In this aspect, X-filling helps to obtain such test patterns. X-filling is to properly assign logic values “0” or “1” to some unspecified bits (referred to as X-bits) in a test pattern based on specific purposes, the test pattern not reducing the fault detection capability for a predetermined semiconductor circuit. For the two test patterns (v1 and v2) shown in FIG. 7, for example, if proper logic values are assigned to the X-bits in the test patterns so that the difference, caused by the patterns (v1 and v2), between the output logic values of each of the gates in a semiconductor circuit is reduced, then IR-drop in the circuit can be reduced. As a result, false testing is also reduced.
Non-patent document 1 describes an X-filling technique for sequentially determining if each of the bits can be turned into an unspecified bit or not, thereby identifying unspecified bits in each test pattern. With this technique, when logic values are assigned to the unspecified bits, only the unspecified bit at a pseudo primary input (test pattern) is considered, while the unspecified bit at a pseudo primary output (test response) is ignored. In addition, Non-patent document 2 describes a technique for identifying arbitrary bits as unspecified bits for all test patterns. With this technique, when logic values are assigned to the unspecified bits, only one bit-pair of a pseudo primary input and a pseudo primary output is considered, and the correlation between the bit-pairs is ignored.
Non-patent document 1: R. Sankaralingam, R. Oruganti, N. Touba, “Reducing Power Dissipation during Test Using Scan Chain Disable,” Proceedings, VLSI Test Symposium, 2001, pp. 319-324
Non-patent document 2: X. Wen, Y. Yamashita, S. Kajiihara, L. T. Wang, K. K. Saluja, K. Kinoshita, “On Low-Capture-Power Test Generation For Scan Testing,” Proceedings, VLSI Test Symposium, May 2005, pp. 265-270